Methods and apparatus to control rail-to-rail class ab amplifiers

ABSTRACT

In one example, an amplifier for providing stable output quiescent current comprising includes a number of supply rails, an output device configured for providing an output voltage, the output device coupled to the plurality of supply rails, and an output quiescent current controller coupled to the plurality of supply rails and the output device, the output quiescent current controller to regulate the voltage in the output device to provide a consistent quiescent current in the output device.

FIELD OF THE DISCLOSURE

This disclosure relates generally to amplifiers, and, more particularly, to methods and apparatus to control rail-to-rail class AB amplifiers.

BACKGROUND

An amplifier is an electronic device that uses transistors or the like to produce an output signal that is an amplified version of an input signal. Types of amplifiers may be broken into classes based on their output performance. For example, class A amplifiers amplify over an entire input cycle such that the output signal is an exact scaled-up replica of the input without clipping, whereas class B amplifiers only amplify half of the input wave cycle. As compared to class A amplifiers, class B amplifiers generate a large amount of output distortion, but have greater efficiencies than do class A amplifiers. A class AB amplifier uses a complimentary pair of class B amplifiers in a push-pull configuration. In such an arrangement, the complementary amplifiers amplify each of the opposite halves of the input signal, which are then recombined at an output. Class AB amplifiers are more efficient than class A amplifiers and have less distortion than class B amplifiers.

Amplifiers can be designed to increase the signal voltage and/or current of an input signal. In terms of supply voltage, amplifiers can operate from double-sided or balanced supplies, which have positive and negative voltage supplies (+ and − supply rails), also referred to as split supplies. The different methods of supplying power result in many different methods of bias to ensure proper operation of the amplifiers. Good control of bias current is necessary because overall current consumption of amplifier devices is a consideration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic illustration of an amplifier including an output quiescent current controller.

FIG. 2 is a schematic illustration of an amplifier having a known output quiescent controller.

FIG. 3 is a block diagram of a further detailed example output quiescent current controller of the amplifier of FIG. 1.

FIG. 4 is a schematic illustration of a further detailed example PMOS output quiescent current controller of the output quiescent current controller of FIG. 3.

FIG. 5 is a schematic illustration of a further detailed example PMOS output quiescent current controller of the output quiescent current controller of FIG. 3.

FIG. 6 is a schematic illustration of a further detailed example output quiescent current controller of the amplifier of FIG. 1.

DETAILED DESCRIPTION

FIG. 1 is a schematic illustration of an example amplifier 100 including an output quiescent current controller 110 and an output stage 112. The example amplifier 100 of FIG. 1 receives power from voltage sources that supply a high voltage supply rail V+ and a low voltage supply rail V− to the output quiescent current controller 110 and the output stage.

As described in further detail below, the output quiescent current controller 110 is configured to match the drain-to-source voltage (Vds) conditions in the output stage 112 to that of associated control transistors within the output quiescent current controller 110 through a closely-coupled current control loop. As shown in FIG. 1, the output quiescent current controller 110 receives input voltages V+ and V− and generates control signals that are coupled to the output stage 112 on lines, or nodes, pmos_gate 114 and nmos_gate 116.

While the following describes numerous configurations that may be used to implement the output quiescent current controller 110 and/or the output stage 112, those having ordinary skill in the art will readily appreciate that variations of the circuit and systems described herein may be used to control the quiescent current of an amplifier. Furthermore, those having ordinary skill in the art will readily appreciate that one or more output stages (e.g., stages like the output stage 112) may be used. The example amplifier may contain a plurality of active devices such as, for example, transistors. A transistor may be of any type of transistor such as, for example, bipolar junction transistor (BJT), field effect transistor (FET) (e.g., complimentary metal-oxide semiconductor transistors (CMOS)), etc. Specifications for each transistor may include, for example, the length of the transistor (1) and the width of the transistor (w). The length of the transistor is the distance from the drain of the transistor to the source of the transistor. A shorter length of the transistor allows for a faster transfer of the signal than across a transistor with a greater length. The width of the transistor refers to the greatest amount of current that is allowed to flow across the transistor. A larger width of the transistor may allow a greater current flow with less loss than a transistor with a more narrow width.

To maintain a relatively constant quiescent current through the output transistors, the example amplifier of FIG. 1 includes an output quiescent current controller 110. As described below, the example output quiescent current controller 110 of FIG. 1 is a circuit having transistors matched to the output stage 112 to automatically set up and hold constant a quiescent current at the output stage 112, independent of the fluctuations of the voltage at either and/or both of the voltage supply rails; ideally at ΔV where ΔV=(V+)−(V−). The output quiescent current controller 110 adjusts the voltage at pmos_gate 114 and nmos_gate 116, thereby setting up a consistent output quiescent current through the transistors in the output stage 112, such that the output quiescent current is matched to the quiescent current within the output quiescent current controller 110. In other words, the output quiescent current controller 110 determines the current flowing through the output stage 112 and adjusts the voltages at and pmos_gate 114 and nmos_gate 116 to achieve a consistent output quiescent current at the output stage 112.

To output a signal, the output stage 112 may be configured to have a Monticelli topology, which is well known to those having ordinary skill in the art. In particular, the output stage 112 may include output transistors 122 and 124, which are respectively PMOS (i.e., p-channel) and NMOS (i.e., n-channel) device that are coupled to the V+ and V− supplies, respectively. The output stage 112 also includes Monticelli bias transistors 126, 128, which are also PMOS and NMOS devices, respectively. The bias and output transistors 126, 128 are configured in a Darlington transistor topology, wherein the PMOS output and bias transistors 122, 126 provide an output for the PMOS portion of the amplifier 100 and the NMOS output and bias transistors 124, 128 provide an output for the NMOS portion of the amplifier 100. Current sources 130 and 132 are respectively coupled to the gates of the output transistors 122, 124, and capacitors 134, 136 are respectively coupled to the gates of the bias transistors 126, 128 and the supply rails.

The source of the output transistor 124 is coupled to the low voltage supply rail V−. The drain of the output transistor 124 is coupled to the drain of the output transistor 122. The current flowing through the output transistors 122 and 124 is represented by iQ. The gate of the output transistor 124 is coupled to the source of the bias transistor 128, to the low voltage supply rail (V−) via the current source 132 (which passes a current of i1), and to the drain of the bias transistor 126. The current flowing through the bias transistor 126 is represented as iD10.

The source of bias transistor 128 is coupled to the gate of output transistor 124, the low voltage supply rail (V−) via current sink 132, and to the drain of the bias transistor 126. The drain of the bias transistor 128 is coupled to the gate of the output transistor 122. The current flowing through the bias transistor 128 is referred to as iD2. The gate of the output transistor 122 is also coupled to the high voltage supply rail V+ via current source 130, and the source of the bias transistor 126. The gate of the bias transistor 128 is coupled to the low voltage supply rail (V−) via the capacitor 136 and is also coupled to the nmos_gate node 116, which is coupled to the output quiescent current controller 110.

The source of output transistor 122 is coupled to the high voltage supply rail (V+). The drain of the output transistor 122 provides an output voltage and is coupled to the drain of the output transistor 124. The gate of the output transistor 122 is coupled to the drain of bias transistor 128 which provides a current referred to as iD2. The gate of the output transistor 122 is also coupled the high voltage supply rail (V+) via the current source 130 and to the source of bias transistor 126.

The source of the bias transistor 126 is coupled to the gate of the output transistor 122 and to the high voltage supply rail (V+) via the current source 130, and the drain of bias transistor 128. The drain of bias transistor 126 is coupled to the low voltage supply rail (V−) via the current sink 132 and the gate of the output transistor 124. The gate of the bias transistor 126 is coupled to the high voltage supply rail (V+) via the capacitor 134 and to the node pmos_gate 114.

Further detail regarding an example output stage 112 is shown in FIG. 2, which shows a known topology of an output quiescent current controller at reference numeral 201. The output quiescent current controller 201 includes a current source 202 and biasing transistors 210, 212. Additionally, the output quiescent current controller 201 includes a current source 208 and biasing transistors 204, 206. The topology of FIG. 2 forms two translinear loops. A first translinear loop is formed from V+ through the biasing transistors 204, 206, through the bias transistor 126 and through the output transistor 122 back to V+. The second translinear loop is formed from V− through the bias transistors 212, 210, through the bias transistor 128 and through the output transistor 124 back to V−.

This topology results in a situation in which a small variation in Vds, results in a large variation in drain-to-source current; this is known as the Early effect. As shown in FIG. 2, the gate of the transistor 126 is two gate-to-source voltage drops (2 Vgs) below the supply voltage V+. The intent of this circuit is to have transistor 204 matched to 122, and 206 matched to 126. However, the Vds of both 204 and 206 is one Vgs for each. The Vds of 126 is approximately the supply voltage minus 2 Vgs's, or ΔV−2 Vgs. The Vds of transistor 122 is approximately ΔV/2. Hence, for ΔV>> than 2 Vgs, the Vds of 122 and 126 do not match 204 and 206 respectively. As ΔV is increased, the gate voltage of 206 remains approximately fixed, but due to the Early effect (or channel length modulation effect in CMOS), the current through 122 increases, sometimes dramatically depending on the value of the Early voltage of the output transistors. Hence, the output quiescent current is not constant and approximately independent of the supply voltage. This effect is also present in variations in V− and how the drain-to-source current is affected in the transistors 128 and 124. As will be readily appreciated by those having ordinary skill in the art, as drain current varies, the performance of the amplifier changes.

FIG. 3 is a schematic illustrative of the example output quiescent current controller 110 of FIG. 1 that compensates for variations in supply voltage to eliminate the effect experienced by the topology of FIG. 2. To maintain a constant quiescent current at the output of the PMOS portion of the output device, the example output quiescent current controller 110 of FIG. 1 includes a PMOS output quiescent current controller 302. The example PMOS output quiescent current controller 302 of FIG. 3 controls the current at the output transistor 122 by regulating the voltage at the node pmos_gate 114, which is coupled to the gate of the bias transistor 126, and in the PMOS translinear loop, described in detail below.

During operation, an increase in supply voltage, ΔV, usually results in an increase in current iQ in the PMOS portion of the output stage 112 (e.g., the output transistor 122) The example PMOS output quiescent current controller 302 of FIG. 3 then provides more voltage to the pmos_gate 114 and, accordingly, to the gate of the bias transistor 126 of FIG. 1. Thus, the bias transistor 126 and the output transistor 122 pass less current and the quiescent current iQ is held constant at the output of the PMOS portion of the output stage 112, thereby producing more consistent amplifier characteristics as the supply voltage varies. Conversely, as a decrease in current is detected in the PMOS portion of the output stage 112, the PMOS output quiescent current controller 302 of FIG. 3 provides less voltage to the pmos_gate 114 of FIG. 1, thus increasing the current flowing through the bias transistor 126 and, therefore, the current through the output transistor 122. Therefore, the quiescent current is held constant at the output in the PMOS portion of the output device producing consistent amplifier characteristics as the supply voltage varies.

To maintain a constant quiescent current at the output of the NMOS portion of the output device (e.g., the output transistor 124), the example output quiescent current controller 110 of FIG. 1 includes an NMOS output quiescent current controller 304, as shown in FIG. 3. The example NMOS output quiescent current controller 304 of FIG. 3 controls the current through the output transistor 124 by regulating the voltage at the nmos_gate 132 and in the NMOS translinear loop, described in detail later, which in turn control the current through the output transistor 124.

During operation, an increase in supply voltage, ΔV, usually results in an increase in current iQ in the NMOS portion of the output device The example NMOS output quiescent current controller 304 then provides less voltage to the nmos_gate 116 of FIG. 1, thereby reducing the amount of current passed through the bias transistor 128. Thus, the quiescent current iQ is held constant at the output of the NMOS portion of the output device producing more consistent amplifier characteristics as the supply voltage varies. On the other hand, as a decrease in current iQ is detected in the NMOS portion of the output device (e.g., in the output transistor 124), the NMOS output quiescent current controller 304 provides more voltage to the nmos_gate 116 of FIG. 1. The voltage increase at the gate of the bias transistor 128 increases the current passed therethrough. Thus, the quiescent current is held consistent at the output in the NMOS portion of the output device producing consistent amplifier characteristics as the supply voltage varies.

FIG. 4 is a schematic illustrative of the example PMOS output quiescent current controller 302 of FIG. 3. To control the current at the output of the PMOS portion of the output device, the PMOS output quiescent current controller 302 of FIG. 3 may include, among other things, transistor(s), current sink(s), current source(s) and/or resistor(s).

The PMOS output quiescent current controller 302 may contain an n-channel cascode transistor 402 having a gate that is set at approximately 1 volt above the desired voltage at the low voltage supply rail V−, herein referred to as Vcasc2. The drain of a transistor Q15 is coupled to a resistor R2 which in turn is coupled to the low voltage supply rail V−. The gate of the transistor Q15 is set to the drain of the transistor Q15. The source of the transistor Q15 is coupled to the drain of a transistor Q16. The gate of the transistor Q16 is set by the drain of the transistor Q16. The source of the transistor Q16 is coupled to a resistor R1, which is coupled to the high voltage supply rail V+. The gate of a transistor Q14 is set at the drain of the transistor Q15, which passes a current defined as iD15. The voltage at the source of a transistor Q15 is V−/2. Hence, the source of transistor Q14 is approximately at the voltage V−/2. In one example, the width of the transistor Q15 is be equal to the width of transistor Q16, and the length of Q15 id to be equal to the length of Q16, as shown in the equations:

W_(Q15)=W_(Q16)

L_(Q15)=L_(Q16)

The drain of the transistor Q14 is coupled to the low voltage supply rail V− via a current sink i10 and shares current with the cascode transistor 402. The source of the transistor Q14 passes current iD14 and is coupled with the low voltage supply rail V− via a current sink i9 and is further coupled to the drain of a transistor Q12.

Turning to the cascode transistor 402, the gate of the cascode transistor, Vcasc2, is set to approximately one volt greater than the desired voltage at the low voltage supply rail V−. The source of the cascode transistor 402 shares the current from the low voltage supply rail V− via the current sink i10 with the drain of the transistor Q14. The drain of cascode transistor 402 is coupled to the gate of a transistor Q11, also referred to as the pmos_gate 114, to the PMOS portion of the output stage 112, and to the high voltage rail V+ via current source i7. A preferred circuit configuration, shown in the following equation, is to have the ratio of the width-to-length ratios of Q14 and Q15 approximately equal to the ratio of the currents iD14 and iD15.

(W/L)_(Q14)/(W/L)_(Q15) =iD14/iD15

As shown in FIG. 4, the drain of the transistor Q12 is coupled to the source of the transistor Q14 and the low voltage supply rail V− via a current sink i9. The source of the transistor Q12 is coupled to the high voltage supply rail V+ and passes a current designated as iD12. The gate of the transistor Q12 is coupled to the source of the transistor Q11. In one example, transistors Q11 and Q12 are designed to match transistors 126 and 122, respectively.

The gate of the transistor Q11 is coupled to the drain of the cascode transistor 402 and to the output device such as, for example, the example Monticelli bias transistor 126 of FIG. 1 via the pmos_gate 114. The gate of Q11 is also coupled to the high voltage supply rail V+ via a current source i7. The source of the transistor Q11 is coupled to the high voltage supply rail V+ via a current source i8 and the gate of the transistor Q12. The drain of the transistor Q11 is coupled to the drain and gate of transistor Q13. So at this point, the drain-to-source voltage (Vds) of the transistor Q11 is equal to the supply voltage ΔV minus the gate-to-source voltage at the transistor Q12 minus the gate-to-source voltage at the transistor Q13, as shown in the equation:

v _(ds) Q11=−ΔV−(v _(gs) Q12+v _(gs) Q13)

The source of the transistor Q13 is coupled to the low voltage supply rail V−. The gate of the transistor Q13 is set by the drain of the transistor Q13. The drain of the transistor Q13 is coupled with the drain of the transistor Q11.

FIG. 5 is a schematic illustration of the example NMOS output quiescent current controller 304 of FIG. 3. To control the current at the output of the NMOS portion of the output device, the NMOS output quiescent current controller 304 may include, among other components, transistor(s), current sink(s), current source(s) and/or resistor(s).

The NMOS output quiescent current controller 304 of FIG. 5 may include a p-channel cascode transistor 502 having a gate voltage (Vcasc1) that is set at approximately 1 volt below that of the high voltage supply rail V+.

The drain of the transistor Q7 is coupled to a resistor R3, which in turn is coupled to the high voltage supply rail V+. The gate of the transistor Q7 is connected to the drain of the transistor Q7. The source of the transistor Q7 is coupled to the drain of the transistor Q8. The gate of the transistor Q8 is set by the drain of the transistor Q8. The source of the transistor Q8 is coupled to a resistor R4 that, in turn, is coupled to the low voltage supply rail V−. The current flowing though R3, R4, Q7, and Q8 is designated as iD7. The gate of the transistor Q6 is coupled to the gate and drain of Q7. Thus, the voltage at the gate of Q8 is ΔV/2. In some examples, the width of the transistor Q7 must be equal to the width of the transistor Q8, and the length of Q7 must be equal to Q8, as shown in the following equations:

W_(Q7)=W_(Q8)

L_(Q7)=L_(Q8)

The drain of the transistor Q6 is coupled to the high voltage supply rail V+ via current source i5 and shares current with the cascode transistor 502. The source of the transistor Q6, is coupled with the high voltage supply rail V+ via current source i4 and further coupled to the drain of the transistor Q4.

Turning to the cascode transistor 502, the gate of the cascode transistor 502 is set to approximately 1 volt less than the desired voltage at the high voltage supply rail V+. The source of the cascode transistor 502 shares the current from the high voltage supply rail V+ via current source i5 with the drain of the transistor Q6. The drain of the cascode transistor 502 is coupled to the gate of the transistor Q3, also referred to as the nmos_gate 116, which is coupled to the bias transistor 128 of the output stage 112, and to the low voltage supply rail V− via current sink i2. A preferred circuit configuration, shown in the following equation, is to have the ratio of the width-to-length ratios of Q6 and Q7 approximately equal to the ratio of the currents iD6 and iD7.

(W/L)_(Q14)/(W/L)_(Q15) =iD14/iD15

As explained above, the drain of the transistor Q4 is coupled to the source of the transistor Q6 and coupled with the high voltage supply rail V+ via current source i4. The source of the transistor Q4 is coupled to the low voltage supply rail V. The gate of the transistor Q4 is coupled to the source of the transistor Q3. In one example, the transistors Q3 and Q4 are designed to match the transistors 128 and 124, respectively.

The gate at the transistor Q3 is coupled to the nmos_gate 116 of FIG. 1. The nmos_gate 116 of FIG. 1 is coupled to the drain of the cascode transistor 502 and to the output device such as, for example, the bias transistor 128 of FIG. 1. The source of the transistor Q3 is coupled to the low voltage supply rail V− via current sink i3 and the gate of the transistor Q4. The drain of the transistor Q3 is coupled to the drain of the transistor Q5. The drain-to-source voltage of the transistor Q3 is equal to the supply voltage ΔV minus the gate-to-source voltage at the transistor Q4 minus the gate-to-source voltage at the transistor Q5, as shown in the equation:

v _(ds) Q3=ΔV−(v _(gs) Q4+v _(gs) Q5)

The source of the transistor Q5 is coupled to the high voltage supply rail V+. The drain of the transistor Q5 is set by the gate of the transistor Q5. The drain of the transistor Q5 is coupled with the drain of the transistor Q3.

FIG. 6 is a detailed schematic illustration of the circuits of FIGS. 4 and 5 coupled with an output stage, such as the output stage 112 of FIG. 1. Relative values are shown for transistor sizes and currents where appropriate. Those having ordinary skill in the art will readily appreciate that such values are merely relative examples. A translinear loop is described for the NMOS and PMOS portions of the output of the amplifier. As the voltage at the rails vary, the feedback portion of the output quiescent current controller detects the increase or decrease in voltage in the translinear loop and adjust the voltage at the NMOS and/or PMOS gates to regulate the voltage and, thus, control the quiescent current at the output stage 112. The amplifier 100 will be described from the NMOS portion followed by the PMOS portion.

Turning to the NMOS portion of the amplifier, an NMOS translinear loop is set up where the source of the transistor 124 is coupled to the low voltage supply rail V−. The gate of the transistor 124 is coupled to the source of the transistor 128. The gate of the transistor 128 is coupled to the gate of the transistor Q3. The source of the transistor Q3 is coupled to the gate of the transistor Q4 and the source of the transistor Q4 is coupled to the low voltage supply rail V−. In one implementation, the translinear loop has the characteristic that the length of the transistor 124 and the length of the transistor Q4 are approximately equal and the width of the two the transistors, 124 and Q4, are proportional. Likewise, the length of the transistor 128 and the length of the transistor Q3 are approximately equal and the width of the two the transistors, 128 and Q3, are proportional.

The current through the transistor Q3 is precisely set by current sink i3. The Vds of Q3 is set by Q4 and Q5 and is closely matched to that of 128. That is, the drain-to-source voltage at the transistor Q3 is equal to the supply voltage ΔV—the gate-to-source voltage at the transistor Q4—the gate-to-source voltage at the transistor Q5, as shown in the equation:

v _(ds) Q3=ΔV−(v _(gs) Q4+v _(gs) Q5)

Because the gate of the transistor Q3 is coupled to the gate of the transistor 128 where the source of the transistor 128 is coupled to the gate of the transistor 124 and the drain of the transistor 128 is coupled to the gate of the transistor 122, the drain-to-source voltage at the transistor 128 is virtually the same as the drain-to-source voltage of transistor Q3. Therefore the Vds of transistor 128 matches that of transistor Q3.

To bias the output to the mid-rail (i.e., the point between the high voltage supply rail and the low voltage supply rail, ΔV/2) the drain-to-source voltage of the transistor Q4 must also match the drain-to-source voltage of the transistor 124 when no signal is being passed through the transistor 128 and 124, in other words the drain-to-source voltage of the transistor Q4 is ΔV/2.

To establish a voltage at the mid-rail, resistor R3 and resistor R4 are equal, the voltage across the transistor Q7 and the transistor Q8 are equal and the gate-to-source voltage across the transistor Q6 must be approximately the same as that of the transistors Q7 and Q8. The source of the transistor Q6 is the same as the source of the voltage at the transistor Q7, so the source of the transistor Q6 is ΔV/2 and is coupled to the drain of the transistor Q4. Thus the drain-to-source voltage of the transistor Q4 is established. The transistor Q4 then must have its current set up. By adjusting the current at the transistor Q4 the current at iQ is also adjusted accordingly.

To set up the current at the transistor Q4, the current at current source i5 is split to the drain of the transistor Q6 and to the source of the cascode transistor 502. The gate of the cascode transistor 502 is set to a steady voltage of the desired voltage at the high voltage supply rail V+−˜1 volt. The current flowing through the cascode transistor 502 flows to the gate of the transistor bias transistor 128 and the gate of the transistor Q3. Therefore, the current at iD6 must be equal to the current at the high voltage supply rail V+ via current source i5 minus the current flowing to the lower voltage supply rail V− via current sink i2, as shown in the equation:

iD6=i5−i2

The current at iD6 is summed with the current flowing through i4 to the drain of the transistor Q4. Therefore the current flowing from the source of the transistor Q4 must be equal to the current flowing through iD6 plus the current flowing from the high voltage supply rail V+ via current source i4, as shown in the equation:

iD4=iD6+i4

To ensure proper biasing, the feedback voltage at the gate of the transistor Q3 must occur. So, if the voltage at the drain of the transistor Q4 is too low, i.e. the voltage at the gate of the transistor Q4 is too high, the source of the transistor Q6 is pulled down. This results in more current flowing through the transistor Q6 taking most of the current from current source i5, allowing less current to flow through the cascode transistor 502 to the gate of the transistor Q3, thereby decreasing the voltage at the gate of Q3. Likewise, if the voltage at the drain of the transistor Q4 is too high, i.e. the voltage at the gate of the transistor Q4 is too low; the voltage at the source of the transistor Q6 is pulled up. This results in less current flowing through the transistor Q6 thereby allowing most of the current from current source i5 to flow through the cascode transistor 502, thereby increasing the voltage at the gate of the transistor Q3.

If the current at the cascode transistor 502 is less than the current at current sink i2, the voltage is increased at the gate of the transistor Q3, thus pulling up the gate of Q4, until the current at the cascode transistor 502 is equal to the current at i2. Thus, the current is regulated through the transistor Q4, and because Q4 is matched both geometrically and in its Vds to 124, the quiescent current at the output is held approximately constant.

Now, turning to the PMOS portion of the amplifier, a PMOS translinear loop is set up where the source of the transistor 122 is coupled to the high voltage supply rail V+. The gate of the transistor 122 is coupled to the source of the transistor 126. The gate of the transistor 126 is coupled to the gate of the transistor Q11. The source of the transistor Q11 is coupled to the gate of the transistor Q12 and the source of the transistor Q12 is coupled to the high voltage supply rail V+. In one implementation of the translinear loop, the length of the transistor 122 and the length of the transistor Q12 are approximately equal and the width of the two transistors, 122 and Q12, are approximately proportional. Likewise, the length of the transistor 126 and the length of the transistor Q11 are approximately equal and the width of the two transistors, 126 and Q11, are approximately proportional.

The current through the transistor Q11 is precisely set by the current source i8. the Vds of Q11 is set by Q12 and Q13 and is closely matched to that of 126. That is, the drain-to-source voltage at the transistor Q11 is equal to the supply voltage ΔV—gate-to-source voltage at the transistor Q12—the gate-to-source voltage at the transistor Q13, as shown in the equation:

v _(ds) Q11=ΔV−(v _(gs) Q12+v _(gs) Q13)

Because the gate of the transistor Q11 is coupled to the gate of the transistor 126 where the source of the transistor 126 is coupled to the gate of the transistor 122 and the drain of the transistor 126 is coupled to the gate of the transistor 124, the drain-to-source voltage at the transistor 126 is virtually the same as the drain-to-source voltage at the transistor Q11. Therefore, the Vds of transistor 126 matches that of transistor Q11.

To bias the output to the mid-rail (i.e., the point between the high voltage supply rail and the low voltage supply rail, ΔV/2) the drain-to-source voltage of the transistor Q12 must match the drain-to-source voltage of the transistor 122 when no signal is being passed through the transistor 122, in other words the drain-to-source voltage of the transistor Q12 must be ΔV/2. To establish a voltage at the mid-rail, resistor R1 and resistor R2 must be equal, the voltage across the transistor Q15 and the transistor Q16 are equal (i.e. ΔV/2) and the gate-to-source voltage across the transistor Q14 must be approximately the same as that of the transistors Q15 and Q16. The source of the transistor Q14 is the same as the source of the voltage at the transistor Q15, so the source of the transistor Q14 is V−/2 and is coupled to the drain of the transistor Q12. Thus, the drain-to-source voltage of the transistor Q12 is established. The transistor Q12 then must have its current set up. By adjusting the current at the transistor Q12 the current at iQ is also adjusted accordingly.

To set up the current at the transistor Q12, the current at current sink i10 is split to the drain of the transistor Q14 and to the source of the cascode transistor 402. The gate of the cascode transistor 402 is set to a steady voltage of the desired voltage on the low voltage supply rail V−+˜1 volt. The current flowing through the cascode transistor 402 flows to the gate of the transistor 126 and the transistor Q11. Therefore, the current at iD14 is equal to the current at the low voltage supply rail V− via current sink i10 minus the current flowing to the high voltage supply rail V+ via current source i7, as shown in the equation:

iD14=i10−i7

The current at iD14 is summed with the current flowing through current sink i9 to the drain of the transistor Q12, therefore the current flowing from the source of the transistor Q12 is equal to the current flowing through iD16 plus the current flowing from the low voltage supply rail V− via current sink i9, as shown in the equation:

iD12=iD14+i9

To ensure proper biasing, the feedback voltage at the gate of the transistor Q11 must occur. So, if the voltage at the drain of the transistor Q12 is too low, i.e. the voltage at the gate of the transistor Q12 is too high, the voltage at the source of the transistor Q14 is pulled down. This results in less current flowing through the transistor Q14 taking less current from current sink i10, allowing most of the current to flow through the n-channel cascode transistor 402, thereby decreasing the voltage at the gate of Q11. Likewise, if the voltage at the drain of the transistor Q12 is too high, i.e. the voltage at the gate of the transistor Q12 is too low; the voltage at the source of the transistor Q14 is pulled up. This results in more current flowing through the transistor Q14 taking most of the current from i10 allowing less current from current sink i10 to flow through the cascode transistor 402 increasing the voltage at the gate of the transistor Q11.

If the current at the cascode transistor 402 is less than the current at current source i7, the voltage is increased at the gate of the transistor Q11 until the current at the cascode transistor 402 is equal to the current at current source i7. Thus, the current is regulated through the transistor Q12, and because Q12 is matched both geometrically and in its Vds to 122, and the quiescent current at the output is held approximately constant.

Although certain apparatus constructed in accordance with the teachings of the invention have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers every apparatus, method and article of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents. 

1. An amplifier for providing stable output quiescent current comprising: a plurality of supply rails; an output device configured for providing an output voltage, the output device coupled to the plurality of supply rails; and an output quiescent current controller coupled to the plurality of supply rails and the output device, the output quiescent current controller matched to the output device to regulate the voltage in the output device to provide a consistent quiescent current in the output device.
 2. An amplifier as defined in claim 1, wherein: the output device comprises a first n-channel transistor coupled to a low voltage supply rail, wherein a drain of the first n-channel transistor is configured to provide an output of the amplifier, and a second n-channel transistor wherein a source of the second n-channel transistor is coupled to a gate of the first n-channel transistor, and the output quiescent current controller comprises a third n-channel transistor wherein a gate of the third n-channel transistor is coupled to a gate of the second n-channel transistor and a fourth n-channel transistor wherein a gate of the fourth n-channel transistor is coupled to a source of the third n-channel transistor and a source of the fourth n-channel transistor is coupled to the low voltage supply rail, wherein during operation a drain to source voltage of the second n-channel transistor is approximately the same as a drain to source voltage of the third n-channel transistor and wherein the drain to source voltage of the second n-channel transistor and the drain to source voltage of the third n-channel transistor track one another during quiescent operation.
 3. An amplifier as defined in claim 2, wherein during operation a drain to source voltage of the first n-channel transistor is approximately the same as a drain to source voltage of the fourth n-channel transistor and wherein the drain to source voltage of the first n-channel transistor and the drain to source voltage of the fourth n-channel transistor track one another during quiescent operation.
 4. An amplifier as defined in claim 3, wherein the low voltage supply rail and the first, second, third, and fourth n-channel transistors form a translinear loop.
 5. An amplifier as defined in claim 4, further comprising a a constant current source having a first terminal coupled to a high voltage supply rail, and having a second terminal; a fifth n-channel transistor having a drain coupled to the second terminal of the constant current source and having a source coupled to a drain of the fourth n-channel transistor; and a cascode transistor having a source coupled to the second terminal of the constant current source and the drain of the fifth n-channel transistor and having a drain coupled to the gate of the third n-channel transistor and the gate of the second n-channel transistor.
 6. An amplifier as defined in claim 5, wherein a voltage at the gate of the third n-channel transistor controls a drain to source voltage of the fourth n-channel transistor.
 7. An amplifier as defined in claim 6, wherein during operation the drain of the fourth n-channel transistor is a voltage approximately mid-way between the low voltage supply rail and a high voltage supply rail.
 8. An amplifier as defined in claim 7, wherein during operation a gate of the fifth n-channel transistor is a voltage approximately one gate to source voltage drop above the voltage approximately mid-way between the low voltage supply rail and the high voltage supply rail.
 9. An amplifier as defined in claim 8, wherein a length of the first n-channel transistor approximately matches a length of the fourth n-channel transistor and a width of the first n-channel transistor is proportional to a width of the fourth n-channel transistor.
 10. An amplifier as defined in claim 9, wherein a length of a second n-channel transistor approximately matches a length of the third n-channel transistor and a width of the second n-channel transistor is proportional to a width of the third n-channel transistor.
 11. An amplifier as defined in claim 1, wherein: the output device comprises a first transistor coupled to a supply rail, wherein a drain of the first transistor provides an output of the amplifier, and a second channel transistor wherein a source of the second transistor is coupled to a gate of the first transistor, and the output quiescent current controller comprises a third transistor wherein a gate of the third transistor is coupled to a gate of the second transistor and a fourth transistor wherein a gate of the fourth transistor is coupled to a source of the third transistor and a source of the fourth transistor is coupled to the supply rail, wherein a drain to source voltage of the second transistor is approximately the same as a drain to source voltage of the third transistor and wherein the drain to source voltage of the second transistor and the drain to source voltage of the third transistor track one another during quiescent operation.
 12. An amplifier as defined in claim 11, wherein the first, second, third, and fourth transistors comprise n-channel transistors and the supply rail comprises a low voltage supply rail.
 13. An amplifier as defined in claim 11, wherein the first, second, third, and fourth transistors comprise p-channel transistors and the supply rail comprises a high voltage supply rail.
 14. An amplifier as defined in claim 11, wherein the first and fourth transistors match.
 15. An amplifier as defined in claim 1, wherein: the output device comprises a first transistor coupled to a low voltage supply rail, wherein the first transistor provides an output of the amplifier, and a second transistor wherein the second transistor is coupled to the first transistor, and the output quiescent current controller comprises a third transistor wherein the third transistor is coupled to the second transistor and a fourth transistor coupled to the third transistor and the fourth transistor is coupled to the low voltage supply rail, wherein a device output voltage of the second transistor is approximately the same as a device output voltage of the third transistor and wherein the device output voltage of the second transistor and a device output voltage of the third transistor track one another during quiescent operation.
 16. An amplifier as defined in claim 15, wherein the first and fourth transistors match and wherein the second and third transistors match.
 17. An amplifier as defined in claim 16, wherein the first and fourth transistors comprise metal oxide semiconductor transistors.
 18. An amplifier as defined in claim 16, wherein the second and third transistors comprise metal oxide semiconductor transistors.
 19. An output quiescent current controller configured to operate with an output stage having an output transistor and a Monticelli bias transistor, the output quiescent current controller comprising: a first transistor having a width that is approximately the same as a width of the output transistor; a second transistor having a width that is approximately the same as a width of the Monticelli bias transistor; a constant current source having a first terminal coupled to a high voltage supply rail, and having a second terminal; a third transistor having a drain coupled to the second terminal of the constant current source and having a source coupled to a drain of the first transistor; and a cascode transistor having a source coupled to the second terminal of the constant current source and the drain of the third transistor and having a drain coupled to a gate of the second transistor.
 20. An output quiescent current controller as defined in claim 19, wherein the Monticelli bias transistor and the second transistor comprise metal oxide semiconductor technology. 